차세대 반도체 소자 연구실

With the scaling of classical planar bulk MOSFETs into the nanometer regime, suppressing short channel effects using precise channel doping levels and gradients has become challenging. The high level of channel doping degrades the drive current due to carrier mobility degradation and increases off-state current by increasing band-to-band tunneling. Further, the increased junction capacitance of the source/drain degrades speed, while the limited number and location of dopants in the channel induce significant and irreducible statistical variability in the threshold voltage. To overcome these challenges in classical bulk MOSFETs, double-gate FinFETs will be needed to scale CMOS down to the 32 nm technology node and beyond.

Design and optimization of semiconductor device and circuit as described above for the next generation is the main topic of the research in VLSI Circuit & Device Design Lab. To design and examine the novel device and circuit, TCAD and SPICE simulation tools installed in high-end workstation are used. Electrical characterization of the fabricated device is performed using the high-precision measurement system.